VLSI Architecture Based Advanced Encryption Standard (AES) With Optimized Inverse Mix-Column and X-Time Multiplication Process

Authors

  • Azath mubarakali

DOI:

https://doi.org/10.20894/IJMSR.117.009.003.009

Keywords:

Advanced Encryption Standard, Mix-column, Xtime Multiplication, Very Large Scale Integration.

Abstract

Rijndael is the security based methodology used to protect the information from the attackers. Rijndael algorithms perform with the data encryptions and data decryptions. Data Encryption is transform the plain text into the cipher text and the data decryption is recovering the original data. Mix-column and Inverse Mix-column is one of the difficult operations in the Rijndael algorithm. In this paper, Optimized Inverse Mix-Column transformation has been designed with the help of Xtime multiplication process. Xtime multiplication performs the multiplication function for „m X m‟ data; results will be m-bit data. Further the complexity of Xtime multiplication process has been identified and re-designed with the help of effective CSE techniques. Developed Reduced Xtime based optimized Inverse Mix-Column transformation provide better performances than traditional Xtime based Inverse Mix-Column multiplication. The proposed mix column and X-time multiplication design is implemented in terms of the VLSI Design Environment.

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Author Biography

Azath mubarakali

Assistant professor, department of computer Networks and communication Engineering, college of computer Science, king Khalid university, Saudi Arabia.

References

1. Agarwal, A, (2013) “VLSI Implementation of Advanced Encryption Standard using Rijndael Algorithm” International Journal of Application or Innovation in Engineering and Management (IJAIEM).

2. Al-Hazaime, O.M.A, (2013) “A New Approach for Complex Encrypting and Decrypting data” International Journal Computer Networks and Communications (IJCNC).

3. Babu, R. Abraham, G. and Borasia, K. (2012) “Securing Distributed Systems Using Symmetric Key Cryptography”.

4. Liu, B. & Baas, B. M. (2013) “Parallel AES encryption engines for many-core processor arrays” IEEE Transactions on Computers pp. 536-547.

5. Shylashree, N. Bhat, N. & Shridhar, V.(2012) “FPGA implementations of advanced encryption standard: a survey” International Journal of Advances in Engineering & Technology, Vol.3, No.2, pp. 265-285.

6. Standaert, F.X. Rouvroy, G. Quisquater, J. J and Legat, J.D.(2004) “Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware”.

7. Zhao, W. Ha, Y. & Alioto, M. “ AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2349-2352, 2015.

8. Zhang, Q. Cao, J. Yu, D. Cao, X. & Zhang, X. “ A Low-energy high-throughput asynchronous AES for secure smart cards” pp.487-490, 2015.

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Published

2017-10-23

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Section

Articles