Design and Implementation of Efficient Advanced Encryption Standard Composite S-Box with CM-Mode


  • Sharmila M
  • Gunasekaran K



Advanced Encryption Standard (AES), Rijindael Algorithm, Enhanced Mix-Column, S-box, Composite Field Arithmetic (CFA), Very Large Scale Integration (VLSI).


Advanced Encryption Standard is the most popular cryptographic security algorithm used for data protection and transmission. The paper proposes an implementation of the AES new Mix- Column operation. In this paper, an enhanced Mix- Column is designed for AES decryption through Very Large Scale Integration (VLSI) System design environment. In AES Mix-Column, large number of logic gates used to perform the multiplication of input stage bytes (output of shift row) and fixed defined state bytes. In order to decrease this problem, the redundant function of Mix-Column is eliminated and re-designed in this paper. Proposed model of Mix-Column minimizes 25% of logic gates compared with previous work. Further, the proposed Mix-Column of AES decryption achieves by improving the performance of area, delay and power consumption. The implementation of the transformation is optimized and increase speed.


Download data is not yet available.

Author Biographies

Sharmila M

Applied Electronics, Sri Balaji Chockalingam Engineering College, Arni, India.

Gunasekaran K

Professor/ECE Sri Balaji Chockalingam Engineering College,Arni, Tamil nadu, India.


1. DAEMEN, J.—RIJMEN, V.: AES Proposal: Rijndael, The Rijndael Block Cipher, AES Proposal, pp.1–45, 1999 (

2. Balamurugan, J., and Logashanmugam, E. "High speed low cost implementation of advanced encryption standard on FPGA" Current Trends in Engineering and Technology (ICCTET), 2014 2nd International Conference on. IEEE, 2014.

3. Astarloa, A., Zuloaga, A., Lazaro, J., Jimenez, J. and Cuadrado, C. ?Scalable 128-bit AES-CM crypto-core reconfigurable implementation for secure communications? IEEE Applied Electronics, pp. 37-42, 2009.

4. Lee, H., Lee, K. and Shin, Y. ?Implementation and Performance Analysis of AES-128 CBC algorithm in WSNs? Advanced Communication Technology (ICACT), IEEE 2010 The 12th International Conference on Vol. 1, pp. 243-248, 2010.

5. Zhang, X. and Parhi, K.K. ?High-speed VLSI architectures for the AES algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems? Vol. 12, No. 9, pp.957-967, 2004.

6. Arbaugh, William A. ?Real 802.11 security: Wi-Fi protected access and 802.11 i? Addison-Wesley Longman Publishing Co., Inc., 2003.

7. An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists, in Proceedings of the Third Advanced Encryption Standard (AES) Candidate Conference, pp. 13–27 , April, 2000.

8. Hardware Evaluation of the AES Finalists, in Proceedings of the Third Advanced Encryption Standard (AES) Candidate Conference, pp. 297–285, April, 2000.

9. Verbauwhede, I., Schaumont, P. and Kuo, H. Design and performance testing of a 2.29-GB/s Rijndael processor. IEEE Journal of Solid-State Circuits, 38(3), pp.569-572, 2003.

10. Chodowiec, Pawel, Kris Gaj, Peter Bellows, and Brian Schott. "Experimental testing of the gigabit IPSec-Compliant implementations of Rijndael and triple DES using SLAAC-1V FPGA accelerator board." International Conference on Information Security, pp. 220-234. Springer Berlin Heidelberg, 2001.

11. Fu, Y., Lin H., Xuejie, Z. and Rujin Y. "Design of an extremely high performance counter mode AES reconfigurable processor." IEEE Second International Conference on Embedded Software and Systems (ICESS'05), pp. 7-pp, 2005.

12. Vu, K. and Zier, D. FPGA implementation AES for CCM mode encryption using Xilinx Spartan-II. ECE-679, Oregon State University, Spring, 2003.