Design and Analysis of Various Standard Multipliers Using Low Power Very Large Scale Integration (VLSI)
DOI:
https://doi.org/10.20894/IJMSR.117.004.001.007Keywords:
Fast Multiplier, High Speed Adder, Power-Delay Product, Field Programmable Gate Array.Abstract
This paper presents a comparative study of Field Programmable Gate Array (FPGA) implementation of standard multipliers using Verilog HDL. Multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transforms (DCT) and so on. Significant reduction in FPGA resources, delay, and power can be achieved using Reduced Wallace multipliers with Kogge-stone adder instead of standard parallel multipliers.
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References
[1] C.Y.H. Lee. “A Performance Comparison Study on Multiplier Designs,” B.Eng. Project Report, University Technology PETRONAS, 2009.
[2] Chris Y.H. Lee, Lo Hai Hiung, Sean W.F. Lee, Nor Hisham Hamid “A Performance Comparison Study on Multiplier Designs”.
[3] Soojin Kim and Kyeongsoon Cho “Design of High-speed Modified Booth Multipliers Operating at GHz Ranges” World Academy of Science, Engineering and Technology 61 2010.
[4] Habibi and P.A. Wintz. “Fast Multipliers,” IEEE Trans. on Computers, vol. 19, pp. 153-157, 1970.
[5] B.Ramkumar,Harish M Kittur, P.Mahesh Kannan, “ASIC Implementation of Modified Faster Carry Save Adder”, European Journal of Scientific Research, ISSN 1450-216X Vol.42 No.1, pp.53-58, 2010.
[6] S. Shah, A.J. Al-Khalili and D. Al-Khalili. “Comparison of 32-bit Multipliers for Various Performance Measures,” in the 12thInternational Conference on Microelectronics, pp. 75-80, 2000.
[7] P.C.H. Meier, R.A. Rutenbar and L.R. Carley, “Exploring Multiplier Architecture and Layout for Low Power,‟ in IEEE Custom Integrated Circuits Conf., pp. 513-516, 1996.
[8] Kousuke TARUMI, Akihiko HYODO, Masanori MUROYAMA, Hiroto YASUURA, “A design method for a low power digital FIR filter in digital wireless communication systems,” 2004.
[9] K.C. Bickerstaff and E.E. Swartzlander, Jr. “Analysis of Column Compression Multipliers,” in 15thIEEE Symp. On Computer Arithmetic, pp. 33-39, 2001.
[10] Dandapat, S. Ghosal, P. Sarkar, D. Mukhopadhyay”A 1.2-ns16×16-BitBinaryMultiplier Using High Speed Compressors” International Journal of Electrical, Computer, and Systems Engineering 4:3 2010.
[11] C.S. Wallace. “A Suggestion for a Fast Multiplier,” IEEE Trans. on Electronic Computers, vol. EC-13, pp. 14-17, 1964.
[12] L. Dadda. “Some Schemes for Parallel Multipliers,” Alta Frequenza, vol. 34, pp. 349-356, 1965.
[13] K.A.C. Bickerstaff, M. Schulte, and E.E. Swartzlander, Jr., “Reduced Area Multipliers,” Intl. Conf. on Application-Specific Array Processors, pp. 478-489, 1993.
[14] S.Rajaram , Mrs.K.Vanithamani “Improvement of Wallace multipliers using Parallel prefix adders”Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011).
[2] Chris Y.H. Lee, Lo Hai Hiung, Sean W.F. Lee, Nor Hisham Hamid “A Performance Comparison Study on Multiplier Designs”.
[3] Soojin Kim and Kyeongsoon Cho “Design of High-speed Modified Booth Multipliers Operating at GHz Ranges” World Academy of Science, Engineering and Technology 61 2010.
[4] Habibi and P.A. Wintz. “Fast Multipliers,” IEEE Trans. on Computers, vol. 19, pp. 153-157, 1970.
[5] B.Ramkumar,Harish M Kittur, P.Mahesh Kannan, “ASIC Implementation of Modified Faster Carry Save Adder”, European Journal of Scientific Research, ISSN 1450-216X Vol.42 No.1, pp.53-58, 2010.
[6] S. Shah, A.J. Al-Khalili and D. Al-Khalili. “Comparison of 32-bit Multipliers for Various Performance Measures,” in the 12thInternational Conference on Microelectronics, pp. 75-80, 2000.
[7] P.C.H. Meier, R.A. Rutenbar and L.R. Carley, “Exploring Multiplier Architecture and Layout for Low Power,‟ in IEEE Custom Integrated Circuits Conf., pp. 513-516, 1996.
[8] Kousuke TARUMI, Akihiko HYODO, Masanori MUROYAMA, Hiroto YASUURA, “A design method for a low power digital FIR filter in digital wireless communication systems,” 2004.
[9] K.C. Bickerstaff and E.E. Swartzlander, Jr. “Analysis of Column Compression Multipliers,” in 15thIEEE Symp. On Computer Arithmetic, pp. 33-39, 2001.
[10] Dandapat, S. Ghosal, P. Sarkar, D. Mukhopadhyay”A 1.2-ns16×16-BitBinaryMultiplier Using High Speed Compressors” International Journal of Electrical, Computer, and Systems Engineering 4:3 2010.
[11] C.S. Wallace. “A Suggestion for a Fast Multiplier,” IEEE Trans. on Electronic Computers, vol. EC-13, pp. 14-17, 1964.
[12] L. Dadda. “Some Schemes for Parallel Multipliers,” Alta Frequenza, vol. 34, pp. 349-356, 1965.
[13] K.A.C. Bickerstaff, M. Schulte, and E.E. Swartzlander, Jr., “Reduced Area Multipliers,” Intl. Conf. on Application-Specific Array Processors, pp. 478-489, 1993.
[14] S.Rajaram , Mrs.K.Vanithamani “Improvement of Wallace multipliers using Parallel prefix adders”Proceedings of 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies (ICSCCN 2011).
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2012-12-15
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