A Review of Different Multipliers in Digital Circuits

Authors

  • Alexander S

DOI:

https://doi.org/10.20894/IJMSR.117.004.001.001

Keywords:

Serial and parallel multiplier, array multiplier, tree multiplier.

Abstract

Multiplication is one of the basic functions in all digital circuits. It is widely used in digital signal processing (DSP) applications. Hardware resources utilization and processing time required by it are more than addition and subtraction. There are two different kinds of multiplication algorithms known as, serial multiplication algorithms and parallel multiplication algorithm. Serial multiplication schemes are widely used in sequential circuits, it contain feedback loop. Parallel multiplication algorithms often used in combinational circuits, it does not contain feedback structures. This paper presents various multiplier architectures. Multiplier architectures generally classified into two categories, one is “tree” multipliers and another one is “array” multipliers. Tree multipliers add as many partial products in parallel as possible and therefore, are very high performance architectures. Multiplication operation involves generation of partial products and their accumulation. The speed of multiplication can be increased by reducing the number of partial products.

Downloads

Download data is not yet available.

Author Biography

Alexander S

Department of ECE SKR Engineering College, Chennai, Tamil nadu.

References

1. Chidgupkar, P. D., and Karad, M. T., “The implementation of algorithms in digital signal processing”, Global J. of Engineering Education, vol.8, No.2, 2004.

2. Rabey, J. M., Nikolic, B., and Chandrasekhran, A. P., “Digital Integrated Circuits: A Design Perspective”, 2nd Edition, Prentice Hall, pp. 586-594, 2003.

3. Roy, K., and Yeo, K. S., “Low voltage Low-power VLSI Subsystems”, McGraw-Hill, pp.124- 141.

4. MacSorley, O. L., “High speed arithmetic in binary computers”, Proc.IRE, vol.49,pp. 67-91, 1961.

5. Wallace, C. S., “A suggestion for fast multipliers”, IEEE Trans. Electronics Comput., vol. EC-13, pp.14-17, 1964.

6. Fayed, A. A., and Bayoumi, M. A., “A Merged Multiplier-Accumulator for high speed signal processing applications”, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), pp 3212 -3215, 2002.

7. Fatima, I., “Analysis of Multipliers in VLSI” Journal of Global Research in Computer Science.

Downloads

Published

2012-12-15

Issue

Section

Articles