Schematic Design and Spice Synthesis of the Arithmetical Operation
AbstractIn this work, the analysis of hybrid full adder circuit is designed by using Complementary Metal-oxide semiconductor (CMOS) devices. The adder is one of the most required arithmetical functions of the various digital circuits. Full adder is used to perform the three-bit additions of the given inputs. There are various CMOS logic styles are used to build the full adder circuit. In this work, the hybrid full adder is designed by using the transmission gate logic by using CMOS devices. Voltage scaling and reduced transistor size are features of the conventional CMOS architecture. Complementary pass transistor logic (CPL) is another type of logic used to build an adder. The CPL design isn't appropriate for low-power applications. The proposed circuit is implemented by using S- edit in Tanner EDA. The proposed circuit performances are evaluated by using T-spice in Tanner EDA. The proposed full adder is efficiently used for the Arithmetic and logic unit (ALU).
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