Pipelined FFT Architecture Using Single Path Delay Feedback Structure


  • Suman Mishra Professor and Head of the Department, Electronics and Communication Engineering, CMR Engineering College, Hyderabad, India
  • S. Omkumar Associate Professor, Department of Electronics and Communication Engineering, SCSVMV (Deemed University), Kanchipuram, Tamil Nadu, India


In general, FFT architecture is used to convert time domain signal into frequency domain signal. In all transmitter and receiver FFT/IFFT is one of the main process to get a efficient transmission of information. Pipelined FFT provide better computation than compared to parallel FFT. Radix-2 FFT structure is used to compute the 64-point FFT architecture. Single path delay feedback method is used for reduction of butterfly structure. SDF structure provides fast computation than other structures. Radix-2 takes more time to perform the operation, and also it takes more complex multiplier for twiddle factor multiplication. Radix-4 is the improved version of radix-2; it reduces the stages of butterfly operation. Butterfly structures are used to determine frequency response of time domain signals in IFFT and to determine timing response in frequency domain signals. FFT processors can be classified as two categories, as Decimation in Time (DIT) FFT and Decimation in Frequency (DIF) FFT. The Radix-2 structure with SDF is simulated using Modelsim simulator.


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. Jayaram, K. and Arun, C., “Survey Report for Radix 2, Radix 4, Radix 8 FFT Algorithm”, International Journal of Innovative Research in Science, Engineering and Technology (IJIRSET), Vol. 4, No. 7, pp. 5149-5154, 2015.

. Kaivani, A. and Ko, S. B., “Area Efficient Floating Point FFT Butterfly Architectures Based on Multi-operand adders”, Electronics Letters, Vol. 51, No. 12, pp. 895-897, 2015.

. Kang, H. J. Lee, J. Y. and Kim, J. H., “Low Complexity Twiddle Factor Generation for FFT Processor”, Electronics Letters, Vol. 49, No. 23, pp. 1443-1445, 2013.

. Cherkauer, B. S. and Friedman, E. G., “A Hybrid Radix-4/Radix-8 Low Power, High Speed Multiplier Architecture for Wide Bit Widths”, IEEE International Symposium, Vol. 4, pp. 53-56, 1996.

. Qiao, S. Hei, Y. Wu, B. and Zhou, Y. “An area and power efficient FFT processor for UWB systems” In Wireless Communications, Networking and Mobile Computing, 2007. WiCom 2007. International Conference on (pp. 582-585). IEEE, 2007.

. Rajeswari, L.M. and Satis, K.M. “Design of Data Adaptive IFFT/FFT Block for OFDM System” IEEE conference on 2011.

. Srikanth, P.K. and Saranya, C. “Analysis and Implementation of a Low power/High Speed 64 point pipeline FFT/IFFT processor” International Journal of Computational Intelligence and Informatics (IJCII), Vol. 1, No. 3, pp: 216-221, 2011.


. Adiono, T. and Mareta, R., 2012, June. Low latency parallel-pipelined configurable FFT-IFFT 128/256/512/1024/2048 for LTE. In 2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012) (Vol. 2, pp. 768-773). IEEE.

. Bepari, D. and Mitra, D., 2015. Improved power loading scheme for orthogonal frequency division multiplexing based cognitive radio. IET Communications, 9(16), pp.2033-2040.

. Shilpha, G., 2014. Low power 128 point split radix fft for lte application. International Journal of MC Square Scientific Research, 6(1), pp.66-74.

. Jabbar, S.A. and Nampoothiri, N.G., 2016. Design and Analysis of Burst Error Correcting Code for Nanoscale SRAM. International Journal of Engineering Science, 3013.

. Sandyarani, K. and Kumar, P.N., 2016. Extended Hamming SEC-DAED-TAED based Fault Detection Technique for AES Encryption and Decryption. Indian Journal of Science and Technology, 9(33), pp.1-5.

. Rahim, R., 2017. Bit Error Detection and Correction with Hamming Code Algorithm.

. Kamatchi, S., Vivekanandan, C. and Thilagavathi, B., 2017. Detection and Correction of Multiple Upsets in Memories Using Modified Decimal Matrix Code. Journal of Computational and Theoretical Nanoscience, 14(3), pp.1543-1547.