Pipelined FFT Architecture Using Single Path Delay Feedback Structure

Authors

  • Suman Mishra Professor and Head of the Department, Electronics and Communication Engineering, CMR Engineering College, Hyderabad, India
  • S. Omkumar Associate Professor, Department of Electronics and Communication Engineering, SCSVMV (Deemed University), Kanchipuram, Tamil Nadu, India

Abstract

In general, FFT architecture is used to convert time domain signal into frequency domain signal. In all transmitter and receiver FFT/IFFT is one of the main process to get a efficient transmission of information. Pipelined FFT provide better computation than compared to parallel FFT. Radix-2 FFT structure is used to compute the 64-point FFT architecture. Single path delay feedback method is used for reduction of butterfly structure. SDF structure provides fast computation than other structures. Radix-2 takes more time to perform the operation, and also it takes more complex multiplier for twiddle factor multiplication. Radix-4 is the improved version of radix-2; it reduces the stages of butterfly operation. Butterfly structures are used to determine frequency response of time domain signals in IFFT and to determine timing response in frequency domain signals. FFT processors can be classified as two categories, as Decimation in Time (DIT) FFT and Decimation in Frequency (DIF) FFT. The Radix-2 structure with SDF is simulated using Modelsim simulator.

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References

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Published

2021-09-22

Issue

Vol. 13 No. 3 (2021)

Section

Articles

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