Effective Communication Using Adaptive FFT/IFFT

Authors

  • K. Umapathy Associate Professor, Department of Electronics and Communication Engineering, SCSVMV (Deemed University), Kanchipuram, Tamil Nadu, India.
  • Rajmohan M Assistant Professor, Electronics and Communication Engineering, Hindustan Institute of Technology and Science, Chennai, Tamilnadu, India.

Abstract

In any communication system FFT/IFFT is one of the important processes to get an efficient output from the communication system. FFT/IFFT is a process used to convert time signal to frequency signal and frequency signal to time signal. Different FFT/IFFT structures are used to process the signal in different way. But one of the drawbacks in the system is using only one FFT/IFFT process at a time. To improve the system efficiency by using adaptive FFT/IFFT, adaptive technique changes the FFT/IFFT structure based on the signal entering into the system. Single Path Delay Feedback (SDF) and Single path Delay Commutator (SDC) are the two-process used in the system. The frequency domain signal is converted into the time domain using the Inverse Fast Fourier Transformation (IFFT). On the transmitter side, IFFT processors are used to transform the frequency signal (which comes from modulation method) into a time signal. FFT is also used to transform a time domain signal (from a channel decoder) into a frequency domain signal. These kinds of process achieve higher efficiency when compared to the previous system.

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References

Nguyen, K, Zheng, J. He, Y. and Shah, B. “A High-Throughput, Adaptive FFT Architecture for FPGA-Based Space-Borne Data Processors” NASA/ESA Conference on Adaptive Hardware and Systems, pp: 121-126, 2010.

Qiao, S. Hei, Y. Wu, B. and Zhou, Y. “An area and power efficient FFT processor for UWB systems” In Wireless Communications, Networking and Mobile Computing, 2007. WiCom 2007. International Conference on (pp. 582-585). IEEE, 2007.

Rajeswari, L.M. and Satis, K.M. “Design of Data Adaptive IFFT/FFT Block for OFDM System” IEEE conference on 2011.

Srikanth, P.K. and Saranya, C. “Analysis and Implementation of a Low power/High Speed 64 point pipeline FFT/IFFT processor” International Journal of Computational Intelligence and Informatics (IJCII), Vol. 1, No. 3, pp: 216-221, 2011.

Rao, K.H. and Paul, C.K.C., Design Of Area Efficient R2MDC FFT Using Optimized Complex Multiplier.

Adiono, T. and Mareta, R., 2012, June. Low latency parallel-pipelined configurable FFT-IFFT 128/256/512/1024/2048 for LTE. In 2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012) (Vol. 2, pp. 768-773). IEEE.

Bepari, D. and Mitra, D., 2015. Improved power loading scheme for orthogonal frequency division multiplexing based cognitive radio. IET Communications, 9(16), pp.2033-2040.

Shilpha, G., 2014. Low power 128 point split radix fft for lte application. International Journal of MC Square Scientific Research, 6(1), pp.66-74.

Jabbar, S.A. and Nampoothiri, N.G., 2016. Design and Analysis of Burst Error Correcting Code for Nanoscale SRAM. International Journal of Engineering Science, 3013.

Sandyarani, K. and Kumar, P.N., 2016. Extended Hamming SEC-DAED-TAED based Fault Detection Technique for AES Encryption and Decryption. Indian Journal of Science and Technology, 9(33), pp.1-5.

Rahim, R., 2017. Bit Error Detection and Correction with Hamming Code Algorithm.

Kamatchi, S., Vivekanandan, C. and Thilagavathi, B., 2017. Detection and Correction of Multiple Upsets in Memories Using Modified Decimal Matrix Code. Journal of Computational and Theoretical Nanoscience, 14(3), pp.1543-1547.

Kumar, K.R., 2018. A Normal I/O Order Radix-2 FFT Architecture for High Speed Applications.

Liu, S., Reviriego, P., Xiao, L. and Maestro, J.A., 2016. Reducing the cost of triple adjacent error correction in double error correction orthogonal latin square codes. IEEE Transactions on Device and Materials Reliability, 16(2), pp.269-271.

Vinothini, V. and Jebasingh, J.A., 2015. Efficient Error Detection and Correction Using Decimal Matrix Code For Memory Reliability. IJRECE, 3(2), pp.20-23.

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Published

2021-03-27

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