LOW POWER RADIX-2 BASED SINGLE PATH DELAY FEEDBACK FFT WITH DIF ALGORITHM
Abstract
In this paper, describe a processor architecture customized to radix-2 based SDF FFT algorithm. The proposed architecture supports all FFT sizes, required by the OFDM applications. The main goal of the proposed architecture is to reduce the area, latency, power and also to decrease computational path for speed up the FFT processor calculation. The proposed low power radix-2 based single path delay feedback FFT architecture with DIF algorithm applies various periodicity properties of twiddle factors multiplier. In other hand, Decimation in Time (DIT) is mostly used to convert the frequency domain signal into time domain signal. The main goal of the VLSI design is to reduce the hardware utilization, delay, and power consumption of the architecture. Generally, SDF architecture is designed for high-speed applications. It offers less delay during the computation of FFT process to implement the processor in 16-point SDF FFT architecture with DIF algorithm. The processor has been synthesized on a Xilinx ISE 12.4design technology and both area efficiency and performance have been evaluated.Downloads
References
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