Tanner Design for Reversible Multiplier


  • K. Gunasekaran Professor, Electronics and Communication Engineering, Sidhartha institute of Science and Technology,Puttur, Adhra Pradesh, India.


In recent times, power consumption is one of the major drawbacks in both analog and digital circuits. Today all integrated circuits are merged with millions of CMOS transistors. Interconnection of CMOS transistor will drop the power, so to avoid the power without any losses of information. It can design using Mentor graphic tool, one of the famous tool is Tanner EDA mentor graphics. It is clearly showing the power drop at each and every node of the CMOS circuit. Here designs a multiplier for analyzing the multiplier performance. In all digital circuits, the multiplier is a crucial circuit. Tanner EDA mentor graphics provide a new method to build and analyses analogue multipliers. Integrated circuits are made up of millions of transistors and have a large number of wire connections. Multiplier is designed using reversible logic circuit, because it takes less power than the other gates.


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