High Speed Pipelined Architecture for Adaptive Median Filter

Authors

  • Mohamed Mian A

DOI:

https://doi.org/10.20894/IJMSR.117.001.001.007

Keywords:

Salt and Pepper, Adaptive, Pipeline, FIFO, Rank order, Non linear.

Abstract

Low level data processing functions, like FIR filtering, pattern recognition or correlation, where the parallel implementation is supported by architecture matched special purpose arithmetic; high throughput FPGA circuits easily outperform even the most advanced DSP processors. In this paper investigates a high-speed non- linear Adaptive median filter implementation is presented. Then Adaptive Median Filter solves the dual purpose of removing the impulse noise from the image and reducing distortion in the image. Adaptive Median Filtering can achieve the filtering operation of an image corrupted with impulse noise of probability greater than 0.2.

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Author Biography

Mohamed Mian A

Assistant Professor Assistant Professor Department of ECE, Abdul Hakeem College of Engineering and Technology
Vellore, India.

References

1. Zdenek Vasicek, Lukas Sekanina, “Novel Hardware Implementation of Adaptive Median Filters.” IEEE.2015.

2. Olli Vainio, Yrjö Neuvo, Steven, and E. Butner, “A Signal Processor for Median-Based Algorithms”, IEEE Transactions on Acoustics, Speech, Processing, vol .37, no.9, 1989.

3. Bapeswara Rao, V.V, and K. Sankara Rao, “A New Algorithm for Real-Time Median Filtering”, IEEE Transactions on Acoustics, Speech, Processing, vol. 34, no. 6, 1986.

4. Ahmad, M. O, and D. Sundararajan, “Parallel Implementation of a Median Filtering Algorithm”, Int. Symp. on Signals and Systems, 1988.

5. Dobrowiecki Tadeusz, Medián Sz?r?k, and Mérés és Automatika, 37. Évf., 1989. 3.szám

6. Xilinx Foundation Series Quick Start Guide, 1991-1997. Xilinx. Inc

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Published

2009-12-20

Issue

Vol. 1 No. 1 (2009)

Section

Articles

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