• Alexander S



Reversible logic, Multiplier, FIR Filter.


Finite impulse response (FIR) filter is one of the important components in any DSP and communication systems. The output from the DSP processor is depends on the FIR filter, so need an efficient FIR filter design, to achieve an efficient output. Filter architecture contains many components; one of the main components is multiplier. Different types of multipliers are available in the digital circuits, but need an efficient multiplier design to get efficient filters. Multiplier is one of the basic building blocks in the digital circuits. So the performance of the multiplier is important to get an efficient circuit design. Power consumption is one of the major drawbacks in the multiplier. Power consumed by the multiplier is higher in the digital circuits. To overcome the power consumption problem by design an efficient low power multiplier. The low power multiplier is designed by using reversible logic gates. Generally reversible logic was designed by avoiding the higher power consumption by the circuits, compared to Irreversible logic gates, reversible logic consumes less power. To apply the logic in the entire multiplier circuit and see the performance of the multiplier. The low power multipliers overcome the power dissipation in the circuits. It was implemented by using Tanner EDA tool.


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Author Biography

Alexander S

ECE department, SKR Engineering College, Chennai, Tamil nadu.


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