REDUCTION OF RESOURCE USAGE IN FPGA BY IMPLEMENTING BACK PROPAGATION ALGORITHM
DOI:
https://doi.org/10.20894/IJMSR.117.009.001.025Keywords:
Field Programmable Gate Array (FPGA), Microcontrollers. Supervised Learning, VHSIC Hardware Description Language (VHDL), MATLAB.Abstract
Back propagation learning algorithm is used to implementing the FPGA for reducing the memory usage and it is one type of Supervised Learning network. The overfitting problems occurs in the device is obtained by the three steps of the algorithm. The three steps are training, validation and testing. The FPGA implementation is done by the Ex-OR functions and the VHDL code is written for the Ex-OR function using the BP algorithm. Also, the MATLAB code is written for the BP algorithm. The results show that the reducing of resource usage and increase of computational speed by the comparison of the output of VHDL code, Arduino code and MATLAB code. Both of the implementations of the Back-propagation algorithm is useful for applications to real-world problems.
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