FPGA IMPLEMENTATION OF LOW POWER DADDA MULTIPLIERS AND ITS APPLICATION

Authors

  • Vincy Beaulah A

DOI:

https://doi.org/10.20894/IJMSR.117.007.001.003

Keywords:

compressor; Approximate circuit; CMOS; Dadda multiplie; FIR filter.

Abstract

Most of the VLSI circuits used adders as a key portion, since they form a base elements of all arithmetic functions. Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithm. We exhibit a new XOR- XNOR component, based on that 4:2 compressor circuit has been designed. The compressor with modified inbuilt logic is proposed for realizations of multipliers. The aim of this paper is to reduce the power consumption of 4:2 compressor without compromising the performance. Power consumption and delay of dadda multiplier using proposed 4:2 compressor have been compared with earlier reported circuits. In digital signal processing application, the FIR filter is designed based on low power proposed approximate dadda multiplier is presented. Simulations are performed using Xilinx ISE 9.2 and microwind tool based on CMOS technology.

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Author Biography

Vincy Beaulah A

PG Scholar, Department of ECE, Sree Sastha Institute of Engineering and Technology Chembarambakkam, Chennai.

References

[1] Wang Z., Jullien G. A., and Miller W. C., “A new design technique for column compression multipliers,” IEEE Trans. Comput., vol. 44, pp. 962–970, Aug. 1995.

[2] Weste N., Eshranghian K., Principles of CMOS VLSI Design: A System Perspective, Reading MA: Addison-Wesley, 1993.

[3] Zimmermann R. and Fichtner W., “Low-power logic styles: CMOS versus pass - transistor logic,” IEEE J. Solid- State Circuits, vol. 32, pp. 1079–1090, July 1997.

[4] Zhang M., Gu J., and Chang C. H., “A novel hybrid pass logic with static CMOS output drive full-adder cell,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 317–320, May 2003.

[5] Manoj Kumar “Design of Novel 9-Transistor Single Bit Full Adder,” International Conference on Computational Science, Engineering and Information Technology (CCSEIT-2012), Avinashilingam University, Coimbatore, India. pp. 334-337, Oct. 26-28, 2012.

[6] Shams M., Darwish T. K., and Bayoumi M. A., “Performance analysis of low-power 1-bit CMOS full adder cells,”IEEE Trans. VLSI Syst., vol. 10, pp. 20–29, Jan. 2002.

[7] Hsiao S.F., Jiang M.R., Yeh J.S., “Design of high low power 3-2 counter and 4-2 compressor for fast multipliers”, Electronic Letters, Vol. 34, No. 4, pp. 341-343, 1998.

[8] Prasad K., Parhi K.K., “Low power 4-2 and 5-2 compressors”, Proceedings of 35th Asilomar Conference on Signals, Systems and Computers, Vol. 1, pp. 129-133, 2001.

[9] Weinberger A., “4:2 Carry-Save Adder Module”, IBM Technical Disclosure. Bulletin, Vol.23, January 1981.

[10] Momeni A., Han J., Montuschi P., Lombardi F., “Design and analysis of approximate compressors for multiplication,” IEEE Transactions on Computers, in press, 2014.

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Published

2015-12-26

Issue

Vol. 7 No. 1 (2015)

Section

Articles

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