BIST-BASED GROUP TESTING FOR DIAGNOSIS OF EMBEDDED FPGA CORES
DOI:
https://doi.org/10.20894/IJMSR.117.001.001.004Keywords:
Embedded Cores, SOPC, FPGA Testing, Group Testing, DSP Hard Cores.Abstract
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by experiments on the Virtex-5 family of Xilinx FPGAs. High-level HDL code is developed to instantiate a Finite State Machine (FSM) which generates the test inputs for the Blocks Under Test (BUTs). The BUTs are divided into groups of four and at the end of a single stage of testing, up to 2 faulty BUTs are isolated successfully in each group of four. Experiments conducted show efficient fault isolation with a maximum of 30% area overhead under testing conditions. Isolation of faulty DSP cores is rapidly achieved without any permanent area cost. The approach can be readily extended to other embedded cores such as Block RAMs and Multipliers, thus providing a fast, efficient technique for testing prior to System On a Programmable Chip (SoPC) implementation on state of the art SRAM FPGAs.
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2. Y. Zorian, E.J. Marinissen, S. Dey, "Testing Embedded-Core Based System Chips,” Proceedings International Test Conference, pp. 130-141, 1998.
3. K. Saluja, S. Eng, and K. Kinoshita, “ Built-In Self Testing of Embedded Memories,” IEEE Design & Test of Computers, Oct. 1986, pp.27-37.
4. P. Camurati, P. Prinetto, M.S. Reorda, S. Barbagallo, A. Burri, D. Medina, “Industrial BIST of Embedded RAMs,” IEEE Design & Test of Computers, Autumn/Fall 1995, Vol. 12 Issue 3, pp. 86.
5. C. Stroud, P. Chen, S. Konala, and M. Abramovici, “Built-in self-test for programmable logic blocks in FPGAs (finally, a free lunch: BIST without overhead!),” Proc. IEEE VLSI Test Symp., pp. 387-392, 1996.
6. M. Abramovici, C. Stroud, “BIST-Based Test and Diagnosis of FPGA Logic Blocks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.9, No.1, pp. 159-172, 2001.
7. E. Atoofian and Z. Nabavi, “A BIST Architecture for FPGA Look-Up Table Testing reduces Reconfiguration,” Proceeding of the 12th Asian Test Symposium, pp. 84-89, 2003.
8. M. Niamat and P. Mohan, “Logic BIST architecture for FPGAs,” Proceedings of the 44th IEEE Symposium on Circuits and Systems, Vol. 1, pp. 442 – 445, 2001.
9. J. Liu and S. Simmons, “BIST-Diagnosis of Interconnect Fault Locations in FPGAs,” CCECE 2003.
10. A. Doumar and H. Ito, “Detecting, Diagnosing, and Tolerating Faults in SRAM-Based Field Programmable Gate Arrays: A Survey,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.11, No.3, pp. 386-405, June 2003.
11. M. Renovell, J. M. Portal, J. Figueras, Y. Zorian, “Testing the Local Interconnect Resources of SRAM-Based FPGAs,” Journal of Electronic Testing: Theory and Applications, Vol. 16, pp. 513, 520, 2000.
12. C. Stroud, S. Garimella, “Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs,” Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, pp. 130-136, Las Vegas, Nevada, USA, June 2005.
13. S. Garimella, C. Stroud, “A system for Automated Built-In Self-Test of Embedded Memory Cores in System-on-Chip,” Proceedings of the Thirty-Seventh Southeastern Symposium on System Theory, pp. 50-54, 2005.
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