BIST for system-on-a-chip using an embedded FPGA core
Keywords:BIST methodology, FIFO, FGPA
Embedded memories in FPGAs have evolved over each new generation. Several FGPA vendors have sophisticated memories within their devices. Such devices are the Virtex series from Xilinx, the Stratix series from Altera, and the AT40k family of FPGAs from Atmel. These embedded memories are highly programmable and offer the user many options such as selectable word depth and data width. Other modes of operations include built in FIFO support and cascadability with adjacent rams along with several more features.With all of these integrated features, a method for testing this memory resource is required. These algorithms are applicable to testing memory resources in FPGAs. The main concern in testing memory resources is the test time required to detect all faults. Using the latest Virtex 4 FPGA as model, this paper will discuss a BIST methodology for testing memory resources by which a specific set of march tests is used to completely test the memory resource and at the same time minimize the time needed for testing.
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