A BIST TPG for Low Power Dissipation and High Fault Coverage


  • Madhusudhanan R
  • Balarani R




Built-in self-test (BIST), heat dissipation during test application, low power testing, power dissipation during test application, random pattern testing.


In This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3- weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.


Download data is not yet available.

Author Biographies

Madhusudhanan R

Research scholar

Balarani R

Research scholar, SRM University , Chennai.


1.P. H. Bardell, W. H. McAnney, and J. Savir, Built-In Test for VLSI: Pseudorandom Techniques. New York: Wiley, 1987.

2. S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-In test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers,” IEEE Trans. Comput., vol. 44, no. 2, pp. 223–233, Feb.1995.

3. N. Zacharia, J. Rajski, and J. Tyszer, “Decompression of test data using variable-length seed LFSRs,” in Proc. IEEE 13th VLSI Test Symp., 1995, pp. 426–433.

4. S. Hellebrand, S. Tarnick, and J. Rajski, “Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers,” in Proc. IEEE Int. Test Conf., 1992, pp. 120–129.

5. N. A. Touba and E. J. McCluskey, “Altering a pseudo-random bit sequence for scan-based BIST,” in Proc. IEEE Int. Test Conf., 1996, pp. 167–175.

6. M. Chatterjee and D. K. Pradhan, “A new pattern biasing technique for BIST,” in Proc. VLSITS, 1995, pp. 417–425.

7. N. Tamarapalli and J. Rajski, “Constructive multi-phase test point in- sertion for scan-based BIST,” in Proc. IEEE Int. Test Conf., 1996, pp. 649–658.

8. Y. Savaria, B. Lague, and B. Kaminska, “A pragmatic approach to the design of self-testing circuits,” in Proc. IEEE Int. Test Conf., 1989, pp. 745–754.

9. J. Hartmann and G. Kemnitz, “How to do weighted random testing for BIST,” in Proc. IEEE Int. Conf. Comput.-Aided Design, 1993, pp. 568–571.

10. J. Waicukauski, E. Lindbloom, E. Eichelberger, and O. Forlenza, “A method for generating weighted random test patterns,” IEEE Trans. Comput., vol. 33, no. 2, pp. 149–161, Mar. 1989.

11. H.-C. Tsai, K.-T. Cheng, C.-J. Lin, and S. Bhawmik, “Efficient test-point selection for scan-based BIST,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 4, pp. 667–676, Dec. 1998.

12. W. Li, C. Yu, S. M. Reddy, and I. Pomeranz, “A scan BIST generation method using a markov source and partial BIST bit-fixing,” in Proc. IEEE-ACM Design Autom. Conf., 2003, pp. 554–559.

13. N. Z. Basturkmen, S. M. Reddy, and I. Pomeranz, “Pseudo random patterns using markov sources for scan BIST,” in Proc. IEEE Int. Test Conf., 2002, pp. 1013– 1021.

14. Y. Zorian, “A distributed BIST control scheme for complex VLSI devices,” in Proc. VLSI Testing Symp., 1993, pp. 4–9.

15. S. W. Golomb, Shift Register Sequences.Laguna Hills, CA: Aegean Park, 1982.

16. C.-Y. Tsui, M. Pedram, C.-A. Chen, and A.M. Despain, “Low power state assignment targeting two-and multi-level logic implementation,” in Proc. IEEE Int. Conf. Comput.-Aided Des., 1994, pp. 82– 87.

17. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A test vector inhibiting technique for low energy BIST design,” in Proc. VLSI Test. Symp., 1999, pp. 407–412.