A BIST TPG for Low Power Dissipation and High Fault Coverage

Authors

  • Madhusudhanan R
  • Balarani R

DOI:

https://doi.org/10.20894/IJMSR.117.001.001.002

Keywords:

Built-in self-test (BIST), heat dissipation during test application, low power testing, power dissipation during test application, random pattern testing.

Abstract

In This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3- weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS’89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS’89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.

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Author Biographies

Madhusudhanan R

Research scholar

Balarani R

Research scholar, SRM University , Chennai.

References

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Published

2009-12-20

Issue

Vol. 1 No. 1 (2009)

Section

Articles

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