Design and Implementation of Power Efficient Modified Russian Peasant Multiplier using Ripple Carry Adder
Keywords:Modified Russian Peasant Multiplier (MRPM), Ripple Carry Adder (RCA), Partial Product Generation (PPG), Verilog Hardware Description Language (Verilog HDL), and Multiplication and Accumulation unit (MAC).
FIR filters, microprocessor and digital signal processor are the core system of multipliers. MAC is the most important building block in DSP system. The key element of high throughput multiplier and accumulator unit (MAC) is to achieve a high-performance digital signal processing application. In this paper, Modified Russian Peasant Multiplier (MRPM) using Ripple Carry Adder (RCA) has been proposed. According to Russian Rule?s, Divide and conquer technique is used in the multiplication process. But, in perspective of digital design, only shifters and adders are used in Russian Peasant Multiplier to produce Partial Product Generation (PPG). A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the next most significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage. Here, ripple carry adder is used for low power application. Reducing the chip size, increasing the speed and reducing the power consumption are main crucial factors in VLSI System design environment. The goal of this research work is to design the VLSI implementation of MAC for high-speed DSP applications. For designing the Multiplication and accumulation unit, different kinds of multipliers and adders are considered in this paper. The total operation is coded with Verilog HDL using ModelSim 6.3C, synthesized by using Xilinx ISE 12.4i design tool.
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