Reduced Complexity Wallace Tree Mulplier and Enhanced Carry Look-Ahead Adder for Digital FIR Filter

Authors

  • sendhilkumar N C

DOI:

https://doi.org/10.20894/IJMSR.117.009.002.019

Keywords:

Finite Impulse Response (FIR) filter, Multiplication and Accumulation unit (MAC), Reduced Wallace tree multiplier, Carry Look-ahead Adder.

Abstract

Improvement of Digital FIR filter is vital role in the field of Digital Signal
Processing in order to reduce the area, delay and power. MAC (Multiplication and
Accumulation) unit of Finite Impulse Response (FIR) filter has been designed using efficient
Multiplier and adder circuits for Optimized APT (Area, Power and Timing) product. In this
paper, the design of direct form FIR filter with efficient MAC unit has been presented. Initially,
full adder and half adder structures are shrunk down by reducing number of gates. This compact
Full adder and half adder structures are incorporated into reduced Wallace Multiplier and
improved Carry look-ahead Adder. Reduced Wallace tree multiplier and enhanced carry lookahead
adder for digital FIR filter has been proposed in this paper. The proposed 16-bit Carry
look-ahead adder has been improved. Consequently the delay of enhanced Carry look ahead
Adder is reduced. Generation of carry output is performed using number of OR gates in a
sequential manner. All these enhanced architectures are incorporated into the Digital FIR Filter
to reduce the area, delay and power utilization. Simulation results are done by using Modelsim
6.3C and synthesized by Xilinx ISE 10.1i design tool.

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Author Biography

sendhilkumar N C

Assistant Professor, Department of Electronics and Communication Engineering, Sri Indu College of Engineering and Technology, Sheriguda, Hyderabad 70.

References

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[8] Gowrishankar, V. Manoranjitham, D. and Jagadeesh, P. “Efficient FIR Filter Design Using Modified Carry Select Adder & Wallace Tree Multiplier” International Journal of Science Engineering and Technology Research (IJSETR), Vol. 2, No. 3, pp: 703-711, 2013

[9] Dempster, A. G. & Macleod, M. D. “Use of minimum-adder multiplier blocks in FIR digital filters” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol.42, No.9, pp.569-577, 1995.

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Published

2017-08-26

Issue

Vol. 9 No. 2 (2017)

Section

Articles

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