DESIGN OF AREA EFFICIENT R2MDC FFT USING OPTIMIZED COMPLEX MULTIPLIER
DOI:
https://doi.org/10.20894/IJMSR.117.009.002.010Keywords:
Fast Fourier Transform (FFT), Complex multiplier, Radix-2 Multi-path Delay Commutator (R2MDC) FFT, low complexity R2MDC FFT, Very Large Scale Integration (VLSI).Abstract
Fast Fourier Transformation (FFT) algorithm is the frequency transformation technique in which time domain representation of sampled signal is converted into frequency domain representation of sampled one. In this paper, low complexity Radix-2 Multi-path Delay Commutator (R2MDC) FFT frequency transformation technique is developed through Very Large Scale Integration (VLSI) System design environment. Low power consumption, less area and low delay are the main concerns in VLSI. Traditional Radix-2 MDC FFT structure has more hardware complexity due to its intensive computational elements. In general, complex multiplier structure of R2MDC FFT requires more LUTs and slices than other structure. In order to overcome this problem, complex multiplier architecture of R2MDC FFT is effectively optimized in this paper. Proposed optimized complex multiplier architecture consumes less hardware complexity than existing one. Further, design of R2MDC FFT architecture by using optimized complexity multiplier offer more advantages. Simulation results for proposed low complexity R2MDC FFT architecture is evaluated by using Model-Sim6.3C and synthesis results are evaluated by using Xilinx 10.1 design tool.
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