DESIGN OF NOVEL ARCHITECTURE OF FILTER TO REMOVAL OF NOISE IN DIGITAL IMAGE

Authors

  • Kumar charle Paul C

DOI:

https://doi.org/10.20894/IJMSR.117.002.001.004

Abstract

Evolvable hardware (EH) is a new field about the use of evolutionary algorithms (EA). It brings together reconfigurable hardware, artificial intelligence, fault tolerance and autonomous systems. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment This paper represent as a new technique for the design of Adaptive Median Filter within an Evolvable hardware framework, using genetic algorithm (GA), aimed at removing the impulse noise from the image and reducing distortion in the image. This implementation aims at reducing the number of generations required to provide time bound optimal filter configuration and to improve the quality of the filter designed. The GA processing and the Evolvable hardware framework is synthesized on Xilinx . In this paper investigates a high-speed non-linear Adaptive median filter implementation is presented. Then Adaptive Median Filter solves the dual purpose of removing the impulse noise from the image and reducing distortion in the image. Adaptive Median Filtering can achieve the filtering operation of an image corrupted with impulse noise .

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Author Biography

Kumar charle Paul C

Indus college of Engineering, Coimbatore.

References

[1] Zdenek Vasicek, Lukas Sekanina, Novel Hardware Implementation of Adaptive Median Filters 978-1-4244-2277-7/08/ ©2008 IEEE.

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[6] Xilinx Foundation Series Quick Start Guide, 1991-1997. Xilinx. Inc.

[7] Jim Torresen, “An Evolvable Hardware Tutorial”, FPL 2004,821-830.

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[10]. Redmill, D. W., Bull, D. R., and Dagless, E., “Genetic synthesis of reduced complexity filters and filter banks using primitive operator directed graphs”. IEE Proc. Circuits Devices Syst, vol.147, pp. 303-310, 2000. Bull, D. R. and Horrocks, D. H., “Primitive operator digital filters”, IEE Proc. Circuits, Devices and Systems, pp. 401-412, 1991.

[11]. L. Sekanina and P. Mikusek, “Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures”, EvoWorkshops 2008, LNCS 4974, pp. 144–153, 2008.
Evolution Hardware (EH‟05).

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Published

2010-12-18

Issue

Vol. 2 No. 1 (2010)

Section

Articles

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