8-POINT RADIX-8 PIPELINED FFT USING SDF

Authors

  • Geetha P
  • Manimaran A

DOI:

https://doi.org/10.20894/IJMSR.117.009.001.020

Keywords:

Fast Fourier Transform (FFT), Single-path Delay Feedback (SDF) FFT, Very Large Scale Integration (VLSI)

Abstract

Fast Fourier Transform (FFT) operation is one of the most important fundamental operations in the digital signal processing systems. A new pipelined Radix-8 based Fast Fourier Transformation (FFT) architecture is designed for performing frequency transformation techniques. The objective of this design is to improve the speed and to reduce the area, delay and power. Radix-8 FFT, which is used to improve the speed of functioning by reducing the computational path. In the proposed new architecture named as ―Radix-8 SDF FFT‖. In this architecture, the numbers of stages are reduced to 75%. The SDF FFT is to increasing the processing speed of architecture. The performance evaluation of Radix-8 SDF FFT architecture is determined through Very Large Scale Integration (VLSI) system design environment. In the VLSI system design, less area utilization, low power consumption and high speed are the main parameters. Hence, the main goal of proposed architecture is to reduce hardware complexity, power consumption and increasing both speed and throughput of the system. Applications: Mobile Ad-hoc Network (MANET), Orthogonal Frequency Division Multiplexing (OFDM) System.

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Author Biographies

Geetha P

ECE Department (M.E-EST), Karpaga Vinayaga College of Engineering and Technology, G.S.T Road, Mathuranthagam, Kancheepuram District, Tamil Nadu, India.

Manimaran A

Associative Professor (ECE Dept), Karpaga Vinayaga College of Engineering and Technology, G.S.T Road, Mathuranthagam, Kancheepuram District, Tamil Nadu, India

References

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[3]. C.Vennila, G.Lakshminarayanan, Seok-Bum Ko, ―Dynamic PartialReconfigurable FFT for OFDM based Communication Systems‖,Springer Circuit System Signal processing, p 1-18, October 2011.

[4]. Y.-N. Chang, "An efficient VLSI architecture for normal I/O orderpipeline FFT design", IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol.55, No. 12, pp. 1234-1238, Dec. 2008.

[5]. Lenart and Viktor Öwall. Architectures for dynamic data scaling in2/4/8k pipeline FFT cores. IEEE transactions on Very Large ScaleIntegration (VLSI) systems, vol. 14, no. 11, Pages: 1286-1290,November 2006.

[6]. Mian Sijjad Minallah, Gulistan Raja. Real Time FFT ProcessorImplementation. IEEE—ICET 2006 2nd International Conference onEmerging Technologies.Peshawar, Pakistan 13-14, Pages:192-195, November 2006.

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Published

2017-03-27

Issue

Section

Articles