FPGA Implementation of Low Power Dadda Multipliers and its Application

Abstract

Most of the VLSI circuits used adders as a key portion, since they form a base elements of all arithmetic functions. Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithm. We exhibit a new XOR- XNOR component, based on that 4:2 compressor circuit has been designed. The compressor with modified inbuilt logic is proposed for realizations of multipliers. The aim of this paper is to reduce the power consumption of 4:2 compressor without compromising the performance. Power consumption and delay of dadda multiplier using proposed 4:2 compressor have been compared with earlier reported circuits. In digital signal processing application, the FIR filter is designed based on low power proposed approximate dadda multiplier is presented. Simulations are performed using Xilinx ISE 9.2 and microwind tool based on CMOS technology.