Analysis of Frequency Response of RLCNetworks on Sinusoids of Radio Frequencies Leading to Transmission Line Effects On Routing Nets in Very Large Scale Integration Deep-Submicron Circuits

Abstract

VLSI Technology has advanced to the level of transistors fabricated with gate lengths in tens of nanometers. Deep-Submicron VLSI chips need to undergo rigorous post layout simulation tests to ensure the circuit operates as expected even after fabrication. The rules for Layout vs Schematic check is also stringent for such integrated circuits. Chips operating on RF signals have Transmission Line effect along routing wires that leads to additional delays. The nets that behave as transmission lines should also be properly matched. Improper matching leads to power reflection and wastage which is not desirable in portable applications. In this work an analysis is done on nets modeled as Transmission Lines. The behavior of the transmission lines on a range of frequencies is reported in terms of amplitude response and phase response. The behavior of a transmission line depends on the geometry. Based on the information, the geometry and position of routing nets can be optimized to design a routing network with minimum delay.