High Speed Pipelined Architecture for Adaptive Median Filter

Abstract

 Low level data processing functions, like FIR filtering, pattern recognition or correlation, where the parallel implementation is supported by architecture matched special purpose arithmetic; high throughput FPGA circuits easily outperform even the most advanced DSP processors. In this paper investigates a high-speed non- linear Adaptive median filter implementation is presented. Then Adaptive Median Filter solves the dual purpose of removing the impulse noise from the image and reducing distortion in the image. Adaptive Median Filtering can achieve the filtering operation of an image corrupted with impulse noise of probability greater than 0.2.