VLSI BASED Mixed-Radix 8-2 Butterfly FFT with bit reversal for 802.11a

Abstract

OFDM has received a great deal of attention and been adopted in many new generation wideband data communication systems such as IEEE 802.11a. In these communication systems the different applications mentioned above have different demands in operation speed and length of FFT/IFFT. The modified Mixed Radix 8-2 Butterfly FFT with bit reversal for the output sequence derived by index decomposition technique is our proposed VLSI system architecture to design the prototype FFT/IFFT processor for OFDM systems. In this paper the analysis of FFT algorithms such as mixed radix 4-2 and mixed radix 8-2 were designed using VHDL. The results show that the proposed processor architecture can greatly save the area cost while keeping a high-speed processing speed, which may be attractive for many real-time systems. By using the proposed structure, the proposed algorithm makes an offer the simple bit reversal mechanism which is only supported by a fixed radix FFT algorithm