Design of Enhanced Half Ripple Carry Adder for VLSI Implementation of Two-Dimensional Discrete Wavelet Transform

Abstract

This paper presents a systematic high speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High- speed 2-D DWT with computation time as low as N2/12 can be easily achieved for an N X N image with controlled increase of hardware cost. Compared with recently published 2-D DWT architectures with computation time of N2/3 and 2N2/3, the proposed designs can also save a large amount of multipliers and/or storage elements. In proposed DWT models, adders are recognized as high potential than other components. In order to improve the efficiency of DWT process, an efficient adder called “Enhanced Half-Ripple Carry Adder (EHRCA)” has been designed in this research work. Proposed EHRCA circuit offers10.71% improvements in hardware slice utilization, 11.78% improvements in total power consumption than traditional Binary to Excess 1 Conversion (BEC) based Square Root Carry Select Adder (SQRT CSLA)