CMOS Design of Low Power High Speed Hybrid Full Adder

Abstract

In this paper, the design of hybrid full adder CMOS design is presented. There are various design modules are used to implement the hybrid full adder design. Transmission gate logic based hybrid full adder design is implemented in this paper by using complementary metal oxide semiconductor (CMOS) logic for low power applications. In general, the full adder performance evaluation is analyzed for 1 bit and these design bit size is extended up to 4 bit for various applications like ALU Unit. For high speed applications, the proposed design is used and also it reduces the delay and power than existing design. Extended 4-bit full adder is performed with low power voltages and reduced number of transistor counts. There are various logic is used to design a full adder to check the synthesis comparisons through schematic design.Proposed design is designed in S-Edit, these output waveform and simulation results are evaluated in T-Spice by using Tanner EDA Tool.